CONFIG_CLK_SOPHGO_SG2042_PLL: Sophgo SG2042 PLL clock support

General informations

The Linux kernel configuration item CONFIG_CLK_SOPHGO_SG2042_PLL:

• prompt: Sophgo SG2042 PLL clock support
• type: tristate
• depends on: CONFIG_ARCH_SOPHGO || CONFIG_COMPILE_TEST
• defined in drivers/clk/sophgo/Kconfig
• found in Linux kernels: 6.11–6.17, 6.18-rc+HEAD
• modules built: clk-sg2042-pll

Help text

This driver supports the PLL clock controller on the Sophgo SG2042 SoC. This clock IP uses three oscillators with frequency of 25 MHz as input, which are used for Main/Fixed PLL, DDR PLL 0 and DDR PLL 1 respectively.

Hardware

LKDDb

Raw data from LKDDb:

• lkddb module clk-sg2042-pll CONFIG_CLK_SOPHGO_SG2042_PLL : drivers/clk/sophgo/Kconfig : "Sophgo SG2042 PLL clock support" # in 6.11–6.17, 6.18-rc+HEAD
• lkddb of "" "" "sophgo,sg2042-pll" : CONFIG_CLK_SOPHGO_SG2042_PLL : drivers/clk/sophgo/clk-sg2042-pll.c # in 6.11–6.17, 6.18-rc+HEAD
• lkddb platform "clk-sophgo-sg2042-pll" : CONFIG_CLK_SOPHGO_SG2042_PLL : drivers/clk/sophgo/clk-sg2042-pll.c # in 6.11–6.17, 6.18-rc+HEAD

Sources

This page is automaticly generated with free (libre, open) software lkddb(see lkddb-sources).

The data is retrived from:

• Linux kernel
• Linux Kernel Driver DataBase (LKDDb)

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